1. Field of the Invention
The present invention relates to a method of simulating hot carrier deterioration of an MOS transistor, and in particular to a method of simulating hot carrier deterioration of a P-MOS transistor during operation in the FWD and REV modes.
2. Description of the Background Art
Hot carrier deterioration of MOS transistors can be evaluated, for example, based on a rate (.DELTA.Id/Id) of a variation .DELTA.Id of a drain current to an initial drain current Id or a variation .DELTA.Vth of a threshold voltage with respect to an initial threshold voltage Vth.
FIG. 15 is an equivalent circuit diagram showing a concept of the hot carrier deterioration of the MOS transistor which can be found by a conventional simulation method. FIG. 15 shows at (A) a fact that a drain current Id flows in a fresh MOS tr. ansistor before application of a stress. FIG. 15 shows at (B) a fact that a drain current Id' flows through the MOS transistor after hot carrier deterioration. Thus, the hot carrier deterioration changes the drain current flowing through the transistor by .DELTA.Id from the initial drain current Id.
A method of simulating hot carrier deterioration of a P-MOS transistor is described, for example, in IEEE Trans. Electron Devices, Vol. 37, pp 1658-1666 (1990) by Ong et al.
Under a static hot carrier stress condition by a DC (direct current), the hot carrier deterioration rate .DELTA.Id/Id can be expressed by the following formula (101): EQU .DELTA.Id/Id=A.sub.Id .cndot.t.sup.n ( 101)
where t represents a hot carrier stress time, characters "A" and "n" represent coefficients which depend on manufacturing process conditions of transistors and stress conditions.
Under the static hot carrier stress condition by DC, the hot carrier deterioration AVth can be expressed by the following formula (102): EQU .DELTA.Vth=A.sub.Vth .cndot.t.sup.n ( 102)
where t represents a hot carrier stress time, characters "A" and "n" represent coefficients which depend on the manufacturing process conditions of transistors and the stress conditions.
Assuming that a stress time which elapses until the variation rate of drain current attains to (.DELTA.Id/Id).sub.f is a lifetime .tau. of the transistor, the following formula (103) is obtained from the formula (101). For example, the time t at the relationship of (.DELTA.Id/Id).sub.f =10% is defined as the lifetime .tau.. EQU (.DELTA.Id/Id).sub.f =A.sub.Id .cndot..tau..sup.n ( 103)
Assuming that the stress time which elapses until the variation rate of threshold voltage attains to (.DELTA.Vth).sub.f is a lifetime .tau. of the transistor, the following formula (104) is obtained from the formula (102). For example, the time t at the relationship of (.DELTA.Vth).sub.f =10 mV is defined as the lifetime .tau.. EQU (.DELTA.Vth).sub.f =A.sub.Vth .cndot..tau..sup.n ( 104)
For performing a stress acceleration test of P-MOS transistor, the stress conditions applied to the transistor are determined such that the lifetime of transistor attains to the variation rate of (.DELTA.Id/Id).sub.f or (.DELTA.Vth).sub.f defined by the above formula (103) or (104) within a measurable time from about 1 to about 100000 seconds. Measurement is performed in an FWD mode, i.e., with the current flow of the same direction as that of current flow between source and drain in the stressed transistor, and also measurement is performed in an REV mode, i.e., with the current flow of the inverted direction. Thereby, the transistor lifetime related to .DELTA.Id/Id or .DELTA.Vth is obtained at a linear region and a saturated region. The stress voltage used in the acceleration test is determined to set the condition that the hot carrier deterioration quantity attains a maximum value in connection with a certain drain voltage Vd. Thus, in the P-MOS transistor, a gate voltage Vg which maximizes gate current Ig is used.
The above reference (Ong et al.) has proposed a simulation method in which the acceleration test method is expressed in formulas, and the formulas are used for the simulation. According to Ong et al., the lifetime .tau. of P-MOS transistor is expressed by the following experimental formula (105) using the gate current Ig. EQU .tau.=B.cndot.W.sup.m .cndot.Ig.sup.-m ( 105)
where W represents a gate width of the transistor, B represents a coefficient depending on the manufacturing process condition of the transistor, and m represents an index which is deemed to be correlated to impact ionization by hot carriers.
From the formulas (103), (104) and (105), coefficients A.sub.Id and A.sub.Vth can be expresses by the following formulas (106) and (107): EQU A.sub.Id =(.DELTA.Id/Id).sub.f .cndot.(B.cndot.W.sup.-m .cndot.Ig.sup.-m).sup.-n ( 106) EQU A.sub.Vth =(.DELTA.Vth).sub.f .cndot.(B.cndot.W.sup.m .cndot.Ig.sup.-m).sup.-n ( 107)
Therefore, the following formulas (108) and (109) are obtained from the formulas (101), (102), (106) and (107): EQU A.sub.Id =(.DELTA.Id/Id).sub.f .cndot.B.sup.-n .cndot.W-.sup.mn .cndot.Ig.sup.mn .cndot.t.sup.n ( 108) EQU A.sub.Vth =(.DELTA.Vth).sub.f .cndot.B.sup.-n .cndot.W.sup.-mn .cndot.Ig.sup.mn .cndot.t.sup.n ( 109)
For the sake of illustration, the following formula (110) is defined, whereby the formulas (108) and (109) can be changed into the following formulas (111) and (112): EQU F(t)=B.sup.-n .cndot.W-.sup.mn .cndot.Ig.sup.mn .cndot.t.sup.n ( 110) EQU .DELTA.Id/Id=(.DELTA.Id/Id).sub.f .cndot.F(t) (111) EQU .DELTA.Vth=(.DELTA.Vth).sub.f .cndot.F(t) (112)
Thus, F(t) represents a quantity of stress applied from start of application of the hot carrier stress to a time t.
FIG. 16 is a flow diagram showing steps in a method of simulating hot carrier deterioration of a P-MOS transistor utilizing the formula (111) or (112). In this flow diagram, a step S1 includes sub-steps S1a-S1e for extracting unknown parameters in the formula (111) or (112) by a preliminary measuring experiment.
In the sub-step S1a, which is executed for determining the gate current Ig in the formula (106) or (107), an experimental formula Ig=g (Vg, Vd) is determined so that it fits to data related to a plurality of measured points in the preliminary measuring experiment. A lucky electron model, which is an example of determining the gate current Ig, is described in IEEE Trans. Electron Device, Vol. ED-31, September 1984, pp. 1116-1125, by Tam et al.
In the sub-step S1b, transistor parameters such as a mobility .mu.s (i.e., degree of movement) of carriers and a flat band voltage Vfb are extracted before application of the DC stress, for example, using a BSIM (Berkeley Short-Channel IGFET Model) method, which is specifically described by IEEE J. Solid-State Circuits, Vol. SC-22, August 1987, pp 558-566 by Sheu et al. In the subsequent sub-step S1c, the DC stress is applied to the transistor. In the sub-step S1d, the transistor parameters after application of the DC stress are extracted.
Extraction of the transistor parameters before and after application of the DC stress is required for coinciding characteristics of the transistor before application of the stress with characteristics of the transistor obtained by simulation, and is also required for estimating correlation between the actual hot carrier deterioration of the transistor after application of the stress and variation of the transistor parameters.
In the sub-step S1e, the coefficient B and index m are extracted based on comparison of the experimental formula (105) and data related to a plurality of measured points in the preliminary experiment.
In a step 2, the formula (111) or (112) is calculated using the parameters extracted in the step Si, whereby the hot carrier deterioration of P-MOS transistor is simulated.
In the simulation of the hot carrier deterioration of P-MOS transistor according to the prior art described above, the BSI method is used to obtain the transistor parameters after application of the DC stress. The transistor models according to the BSI method, however, do not include a model of lowering of the mobility of carriers, which is caused by the interface level or oxide film trap of electrons due to local hot carrier injection. For the coincidence of transistor characteristics after application of the stress, extraction of parameters is performed with various parameters of mobility .mu.s and flat band voltage Vfb, and the simulation is performed with the parameters thus extracted.
In actual transistors, injection of hot carriers causes a difference between transistor characteristics in the FWD and REV modes as shown in FIGS. 17, 18 and 19.
FIG. 17 is a graph showing an example of Vd-Id characteristics in the FWD mode of the P-MOS transistor. In this figure, the solid curves represent the characteristics before application of the stress, and the broken curves show characteristics after application of the stress.
Likewise, FIG. 18 is a graph showing an example of Vd-Id characteristics in the REV mode of the P-MOS transistor. In this figure, the solid curves represent the characteristics before application of the stress, and the broken curves show characteristics after application of the stress.
FIG. 19 shows Vg-Id characteristics and Vg-gm characteristics in the FWD and REV modes of the P-MOS transistor, where gm represents a mutual conductance. In FIG. 19, the stress conditions were determined such that Ig attained a maximum value with Vd=-6.0V, and the stress was applied for 1000 seconds. Circular marks represent the transistor characteristics before application of the stress, triangular marks represent the transistor characteristics in the FWD mode after application of the stress, and square marks represent the transistor characteristics in the REV mode after application of the stress. The drain current Id was measured under two conditions of Vd=-1.5V and Vd=-0.2V.
A difference between the transistor characteristics in the FWD and REV modes is caused due to the fact that the hot carrier injection locally occurs at the vicinity of the drain in the transistor. Therefore, when using the BSI method which is based on a model that the transistor includes symmetrical source/drain, the transistor parameters after application of the stress must be extracted in both the FWD and REV modes.
According to the conventional simulation, it is impossible to simulate the hot carrier deterioration of transistors such as a pass-transistor in a circuit, which performs a bidirectional operation, i.e., which changes a direction of a current flow between source/drain.